The use of GaAs and GaN HFET devices is increasing because these devices provide high current and high voltage handling capabilities, and thus, these devices are of particular importance in applications that require high power. GaAs and GaN FET type HEMT devices provide high performance over prior known silicon MOSFET devices and this is particularly true in power applications. For example, GaN FET devices have much lower Figure of Merit (FOM) characteristics over silicon MOS devices due to a lower resistance from drain to source when active (Rdson) and lower gate charge (Qg). However, HEMT transistors such as GaN FETs have complex hole and electron trapping characteristics and exhibit current collapse behaviors which, to date, have made test, evaluation and qualification of HEMT and HFET devices difficult, time consuming, and expensive.
The high power capabilities are due to the particular physical characteristics for these devices which have a heterojunction formed in the channel region. For example, for GaN FET devices, the GaN material provides a high breakdown field. Further, the AlGaN/GaN interface provides a high sheet carrier density.
However, unlike conventional silicon MOS devices, GaAS and GaN HFET devices have complex physical characteristics that require additional testing to quantify the performance and thereby qualify FET devices for production. HFET devices exhibit carrier trapping behaviors and high voltage current collapse behaviors that need to be measured for devices in order to qualify production devices for use. These mechanisms are further described, for example, in a paper entitled “Current Collapse in GaN Heterojunction Field Effect Transistors for High-voltage Switching Applications,” presented at the 2014 IEEE International Reliability Physics Symposium (IRPS), Jun. 1-5, 2014, at Waikoloa, Hi., which is hereby incorporated by reference herein in its entirety.
The measurements needed to qualify HFETs are made under a variety of load conditions that, in the prior known solutions, require dedicated circuit boards used in a dedicated custom test environment, adding cost and additional time to the testing process. Further the tests in the prior known solutions are performed on packaged integrated circuit devices. Devices that fail to qualify for use can result in unused silicon and further, wasted package materials including solder balls, wires, mold compound, epoxies and the like.
FIG. 1 depicts, in a cross sectional view, a portion of a prior known as GaN HFET. In FIG. 1, silicon or other semiconductor material substrate 11 is provided. The semiconductor substrate can be of various materials including, for example but without limitation, SiC and sapphire. A buffer layer 13 is provided overlying the substrate. An undoped gallium nitride layer 15 is formed over the buffer layer, for example using epitaxial deposition techniques. An aluminum gallium nitride layer 19 is deposited over the gallium nitride layer 15. In this insulated gate example, a gate dielectric 21 is formed over the aluminum gallium nitride layer; this gate dielectric may be, for example, a silicon nitride layer. A gate conductor 29 is formed over the gate dielectric 29. Source and drain conductors 25 and 23 are formed and contact source and drain regions beneath the conductors in the AlGaN layer. Passivation material 31, 33 overlies and protects the gate dielectric 21, and insulates the conductive source, drain and gate terminals one from another. Because a heterojunction is formed in the channel region beneath the gate electrode, the FET 10 is referred to as an “HFET”.
In operation, the channel for the HFET transistor formed by the gate, source and drain regions has highly mobile electrons in a two dimensional electron gas region formed in a shallow region at the interface between the AlGaN and GaN regions, 17. This region is sometimes referred to as a “2DEG” region.
FIG. 2 depicts a simple circuit symbol for the GaN HFET 10 in FIG. 1. These devices are high power capable FET devices and are useful in application such as bridge circuits and power supply circuits and in forming power amplifiers, for example. In addition the devices are useful at high frequencies and applications include monolithic microwave ICs (MMICs) and microwave and radio frequency circuits.
The HFET transistor 10 in FIG. 2 has a gate, a drain and a source terminal. In testing the HFET devices, complex testing is required due to the current collapse phenomenon. Under certain conditions, the drain current flowing through the HFET device will fall. This current collapse behavior occurs due to carrier trapping mechanisms in the devices that differ from the doped source and drain and the channel operation of conventional silicon MOSFET devices, for example. As a result, a variety of measurements are needed to characterize HFET transistors. Tests are needed to observe the transistors in operation for a variety of different load situations.
FIG. 3 depicts in a graph the drain current vs. drain to source voltage, or “I-V” curves, for a variety of gate voltage VG lines for a typical HFET device. In FIG. 3, a soft switching situation is shown by the line labeled “soft switching”. In soft switching, a gate voltage pulse is applied to an HFET device with little or no voltage at the drain (VD). When an HFET is switched on by a gate pulse with little voltage at the drain terminal, current collapse can occur, that is, the drain current ID can be low or zero even if the HFET device is turned on. In another load situation, known as hard switching, the HFET device can turn on due to a large rise in the gate voltage VG over a threshold voltage while a large voltage is present at the drain (VD). This is indicated in the I-V curves by a line labeled “hard switching”. Finally in another load situation, a resistive load switching can occur, indicated by the line labeled “Resistive load switching,” where the HFET remains in a linear mode, not a saturation mode, and acts as a resistive element, so that the drain current ID falls as the voltage Vds increases (linear resistor).
In a transistor production environment, these HFET devices are tested to qualify the devices for use. To confirm that the finished HFET devices will operate within a certain specified range, the devices can be tested under a range of switching conditions. In the prior known testing solutions, custom circuit boards for controlling the gate and drain voltages were fabricated for the purpose of qualifying the HFET devices. This prior known approach adds expense and testing time to the production process that is greater than normally expended for FET devices. Further, in the prior known approaches the testing to date is done on packaged integrated circuit devices. When a device fails to pass the qualification testing, it is scrapped, and the packaging materials and effort expended in packaging the failed devices can be lost, increasing production costs and wasting mold compound, bond wires, solder bumps, and the like.
Improvements in the methods and apparatus used for qualifying HFET devices such as GaN FETs, for example, are therefore needed to address the deficiencies and the disadvantages of the prior known approaches. Solutions are needed that quickly perform the complex load testing required to qualify these devices at a minimum cost and with no or little custom hardware required.